1. Field of the Invention
The invention relates to protection circuits for complementary symmetry insulated gate (CMOS) field effect transistor integrated circuits. However, the invention also may be used as a protective circuit for single channel MOS field effect transistor integrated circuits.
2. Description of the Prior Art
A particular prior art protection circuit for field effect transistor integrated circuits of which the present invention is an improvement has first and second protective diodes poled with respect to the circuit input terminal so that the anode of the first diode and the cathode of the second diode are coupled to the input, the cathode of the first diode is connected to the drain power supply and the anode of the second diode is connected to the source power supply terminal. A resistance created by the anode region of the first diode exists between the input terminal and cathode of second diode which is also connected to the gate terminals of circuit input field effect transistors. This circuit protects the gate oxide of insulated gate field effect transistors from damage caused by potentials during circuit operation or testing which are applied between the input and either the output, drain power supply V.sub.DD or source power supply V.sub.SS terminals which forward bias the first or second protective diodes. Forward biasing of the protective diodes prevents the application of potentials which could damage the gate oxide of the field effect transistors. The series resistance between input terminals and gate of the input field effect transistors slows the rise of transient potentials on the gate terminal which may be applied to the circuit input terminal.
However, this circuit does not prevent damage caused by high potentials applied between the input and either the output, drain power supply or source power supply terminals which are of a sufficient magnitude to cause excessive currents to flow through the protective diodes when conducting in the avalanche breakdown mode thereby causing destruction of the protective diodes or gate oxide rupture which could destroy the integrated circuit. These potentials are typically produced by electrostatic charges which accumulate on the gate electrodes of the field effect transistors during manufacturing, handling, installation or during tests which are required by customers to simulate those conditions occurring during manufacturing, handling, installation or operation which are most likely to cause rupture of the gate oxide of the field effect transistors to permit identification of failure prone circuits.
In the prior art, two terminal tests have been developed and used by manufacturers of integrated circuits at the request of customers which apply a high potential between the input terminal of an integrated circuit and either the drain supply, source supply or output terminal to test the resistance of protective diodes to breakdown and the resistance of the gate oxide of field effect transistors against rupturing. Such tests are designed and used to simulate the actual application of high electrostatic potentials to the terminals which can occur during manufacturing, handling or installation to permit the identification of those integrated circuits in which the gate oxide would be reptured by high potentials. Such tests will be referred to in this specification as "zap" tests.
The following table identifies those zap potentials which are most likely to cause damage to the protective diodes during avalanche breakdown of the protective diodes or rupture of the gate oxide of the field effect transistors of the prior art protective circuit used to protect CMOS input devices described above. In the table a "+" represents the application of the positive terminal of a high voltage supply to the terminal of an integrated circuit identified under the heading during zap testing. Similarly, a "-" represents the application of the negative terminal of the high voltage supply to the terminal of an integrated circuit identified under the heading during zap testing. An "X" represent that the terminal under the heading is floating during zap testing.
______________________________________ Test No. V.sub.in V.sub.SS V.sub.DD V.sub.out ______________________________________ 1 + - x x 2 - x + x 3 + x x - 4 - x x + ______________________________________
The potential applied during zap testing is typically produced by the discharge of a capacitor, which has been charged to values of 400 and greater volts between the terminals identified in the table described above. The severity of the zap is made greater by higher voltages applied to the capacitor and higher amounts of stored energy, 1/2 cv.sup.2, stored on the discharging capacitor.
From the foregoing table, it is apparent that in zap test 1, the input terminal V.sub.in is connected to the positive terminal of the zap testing apparatus; the source supply terminal V.sub.SS is connected to the negative terminal of the zap testing apparatus and the drain supply terminal V.sub.DD and the output terminal V.sub.out are floating.